(1) Field of the Invention
The present invention relates to the manufacturing of semiconductor memories, and in particular, to forming split-gate flash memories with improved program speed.
(2) Description of the Related Art
Programmability and erasability are important aspects of electrically alterable memory devices as they are well known in the art. The speed of programming and erasing a memory device are governed by the thickness of the tunneling oxide between the substrate and the floating gate and the interpoly oxide between the floating gate and the control gate. At the same time, the thickness of the oxides determine the ease of manufacturability and reliability of semiconductor memories. It is disclosed in the present invention a method of improving the program speed by modifying the thickness of the intergate oxide while at the same time preserving the reliability of the memory device.
In prior art, the importance of program speed and the associated coupling between the floating gate and the source, and between the floating gate and the control gate of a memory cell has been well recognized since the advent of the one-transistor cell memory cell with one capacitor. Over the years, many variations of this simple cell have been advanced for the purposes of shrinking the size of the cell and, at the same time, improve its performance. The variations consist of different methods of forming capacitors, with single, double or triple layers of polysilicon, and different materials for the word and bit lines.
Memory devices include electrically erasable and electrically programmable read-only memories (EEPROMs) of flash electrically erasable and electrically programmable read-only memories (flash EEPROMs). Generally, flash EEPROM cells having both functions of electrical programming and erasing may be classified into two categories, namely, a stack-gate structure and a split-gate structure. A conventional stack-gate type cell is shown in FIG. 1a where, as is well known, tunnel oxide film (20'), a floating gate (30'), an interpoly insulating film (40') and a control gate (50') are sequentially stacked on a silicon substrate (10) between a drain region (13') and a source region (15') separated by channel region (17'). Substrate (10) and channel region (17') are of a first conductivity type, and the first (13') and second (15') doped regions are of a second conductivity type that is opposite the first conductivity type.
One of the problems that is encountered in flash memory of FIG. 1a is the "over-erasure" of the cell contents during erasure operations. In FIG. 1a, the stacked-gate transistor is capable of injecting electrons from drain (13), based on a phenomenon known as the Fowler-Nordheim Tunneling Effect, through tunneling oxide layer (20') into floating gate (30'). The threshold voltage of a stacked-gate transistor can be raised by means of such electron injection, and the device is then assumes a first state that reflect the content of the memory cell. On the other hand, during erasure of the memory cell, electrons are expelled from the source (15') through tunneling oxide layer (20') and out of floating gate (30') of the transistor. As a result of this electron removal, the threshold voltage is lowered and thus the device then assumes a second memory state.
During the process of memory content erasure, however, to ensure complete removal of the electrons previously injected, the erasure operation is normally sustained for a slightly prolonged time period. There are occasions when such a prolonged erasure operation results in the removal of excess electrons, i.e., more electrons than were previously injected. This results in the formation of electron holes in the floating gate of the device. In severe cases, the stacked-gate transistor becomes a depletion transistor, which conducts even in the absence of the application of a control voltage at the control gate, (50). This phenomenon is known in the art as memory over-erasure.
To overcome the described memory over-erasure problem of stacked-gate type EEPROM devices, a split-gate EEPROM device is used as shown in FIG. 1b. This memory device comprises floating-gate transistor which similarly includes control gate (50), floating gate (30) with an intervening interpoly oxide (40) as in the case of the stacked-gate transistor of FIG. 1a. However, floating gate (30) here covers only a portion of the channel region, (17), and the rest of the channel region, (19), is directly controlled by control gate (50). This split-gate-based memory cell is equivalent to a series connected floating-gate transistor (17) and an enhanced isolation transistor (19), as is schematically represented in FIG. 1b. The principal advantage of such configuration is that isolation transistor (19') is free from influence of the state of floating gate (17) and remains in its off-state, even if floating-gate transistor (17) is subjected to the phenomenon of over-erasure and therefore, is in a conductive state. The memory cell can thus maintain its correct state irrespective of the over-erasure problem.
To program the transistor shown in FIG. 1b, charge is transferred from substrate (10) through gate oxide (20) and is stored on floating gate (30) of the transistor. The amount of charge is set to one of two levels to indicate whether the cell has been programmed "on" of "off." "Reading" of the cell's state is accomplished by applying appropriate voltages to the cell source (15) and drain (13), and to control gate (50), and then sensing the amount of charge on floating gate (30). To erase the contents of the cell, the programming process is reversed, namely, charges are removed from the floating gate by transferring them back to the substrate through the gate oxide.
This programming and erasing of an EEPROM is accomplished electrically and in-circuit by using Fowler-Nordheim (F-N) tunneling mentioned above. Basically, a sufficiently high voltage is applied to the control gate and drain while the source is grounded to create a flow of electrons in the channel region in the substrate. Some of these electrons gain enough energy to transfer from the substrate to the floating gate through the thin gate oxide layer by means of (F-N) tunneling. The tunneling is achieved by raising the voltage level on the control gate to a sufficiently high value of about 12 volts. As the electronic charge builds up on the floating gate, the electric field is reduced, which reduces the electron flow. When, finally, the high voltage is removed, the floating gate remains charged to a value larger than the threshold voltage of a logic high that would turn it on. Thus, even when a logic high is applied to the control gate, the EEPROM remains off. Since tunneling process is reversible, the floating gate can be erased by grounding the control gate and raising the drain voltage, thereby causing the stored charge on the floating gate to flow back to the substrate. Of importance in the tunneling region is the quality and the thinness of the tunneling oxide separating the floating gate from the substrate. Usually a thickness of between about 80 to 120 Angstroms is required to facilitate F-N tunneling.
The thicknesses of the various portions of the oxide layers on the split-gate side (between the control gate and the source) and the stacked-side (between the floating gate and the drain) of the memory cell of FIG. 1b play an important role in determining such parameters as coupling ratio and the memory erase-write speed. In prior art, various methods have been developed to address these parameters. For example, in U.S. Pat. No. 5,067,108, Jeng discloses a single transistor electrically programmable and erasable memory cell having a re-crystallized floating gate disposed over a first-insulating layer and extending over a portion of the channel region and over a portion of the drain regions to maximize capacitive coupling therebetween. A second insulating layer has a top wall portion over the floating gate and a side wall portion immediately adjacent to the floating gate and has a thickness which permits Fowler-Nordheim tunneling of charges therethrough. An electrically conductive control gate has two electrically connections sections: A first section is over the first insulating layer and is immediately adjacent to the side-wall portion of the second insulating layer. The first section extends over a portion of the channel region and over the source region. A second section is disposed over the top wall portion of the second insulating layer to minimize capacitive coupling with the floating gate.
Ahn of U.S. Pat. No. 5,652,161 also uses a thick insulation film between the tunneling region and the channel region in an EEPROM split-gate flash memory cell in order to prevent the degradation of the tunnel oxide film due to the band-to-band tunneling and the secondary hot carriers which are generated by a high electric field formed at the overlap regions between the junction region and the gate electrode when programming and erasure operations are performed with high voltage.
Hong, et al., in U.S. Pat. No. 5,422,292 show the forming of an intergate poly between the floating gate and the control gate by using two oxide layers in order to improve the isolation between the two gates and thereby prevent leakage. In a separate U.S. Pat. No. 5,614,747, Ahn, et al., disclose still another method of manufacturing a flash EEPROM cell where over-erasure of a flash EEPROM cell can be prevented and at the same time, the cell area decreased by forming a floating gate in the form of a spacer on a side-wall of a select gate and by forming a control gate to surround the select gate and the floating gate.
In general, prior art makes a trade-off between program speed and erase speed in choosing the various tunnel oxide thicknesses in a memory cell. What is disclosed in the present invention is a method of forming split-gate flash memory cell where program speed can be improved without having to trade-off erase speed.